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ma9264 1/15 the ma9264 64k static ram is configured as 8192x8 bits and manufactured using cmos-sos high performance, radiation hard, 1.5 m m technology. the design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. address input buffers are deselected when chip select is in the high state. see application note overview of the dynex semiconductor radiation hard 1.5 m m cmos/sos sram range. features n 1.5 m m cmos-sos technology n latch-up free n fast access time 70ns typical n total dose 10 6 rad(si) n transient upset >10 11 rad(si)/sec n seu 4.3 x 10 -11 errors/bitday n single 5v supply n three state output n low standby current 100 m a typical n -55 c to +125 c operation n all inputs and outputs fully ttl or cmos compatible n fully static operation operation mode cs ce oe we i/o power read l h l h d out write l h x l d in isb1 output disable l h h h high z standby h x x x high z isb2 xlxx x figure 1: truth table figure 2: block diagram a12 a9 a8 a4 a3 a6 a5 a7 a d d r e s s b u f f e r r o w d e c o d e r a10 a0 a1 a2 a11 cs ce we oe ma9264 radiation hard 8192x8 bit static ram replaces june 1999 version, ds3692-6.0 ds3692-7.0 january 2000
ma9264 2/15 signal definitions a0-12 address input pins which select a particular eight bit word within the memory array. d0-7 bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. cs chip select, which, at low level, activates a read or write operation. when at a high level it defaults the sram to a prechargencondition and holds the data output drivers in a high impedance state. we write enable which when at a low level enables a write and holds data output drivers in a high impedance state. when at a high level, it enables a read. oe output enable which when at a high level holds the data output drivers in a high impedance state. when at a low level, data output driver state is defined by cs , we and ce. if this signal is not used it must be connected to vss. ce chip enable which when at a high level allows normal operation. when at a low level it defaults the sram to a precharge condition, disables the input circuits on all input pins and holds the data output drivers in a high impedance state. if this signal is not used it must be connected to vdd.
ma9264 3/15 characteristics and ratings symbol parameter min. max. units v cc supply voltage -0.5 7.0 v v i input voltage -0.3 v dd +0.3 v t a operating temperature -55 125 c t s storage temperature -65 150 c figure 3: absolute maximum ratings stresses above those listed may cause permanent damage to the device. this is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not implied exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability. notes for tables 4 and 5: characteristics apply to pre radiation at t a = -55 c to +125 c with v dd = 5v 10% and to post 100k rad(si) total dose radiation at t a = 25 c with v dd = 5v 10% (characteristics at higher radiation levels available on request). group a subgroups 1, 2, 3. symbol parameter conditions (option) min. typ. max. units v dd supply voltage - 4.5 5.0 5.5 v v lh logical 1 input voltage - (ttl) v dd /2 - v dd v (cmos) 0.8 v dd -v dd v v ll logical 0 input voltage - (ttl) v ss - 0.8 v (cmos) v ss - 0.2 v dd v v oh1 logical 1 output voltage i oh1 = -2ma 2.4 - - v v oh2 logical 1 output voltage i oh2 = -1ma v dd -0.5 - - v v ol logical 0 output voltage i ol = 4ma - - 0.4 v i li input leakage current v in = v dd or v ss all inputs - - 10 m a i lo output leakage current chip disabled, v out = v dd or v ss -- 10 m a i sb1 selected static current (cmos) all inputs = v dd -0.2v - 0.1 10 ma except cs = v ss +0.2v i dd dynamic operating current f rc = 1mhz, all inputs - 6 18 ma (cmos) switching, v ih = v dd -0.2v i sb2 standby supply current cs = v dd -0.2v - 0.1 10 ma ce = v ss +0.2v figure 4: electrical characteristics symbol parameter conditions (option) min. typ. max. units v dr v cc for data retention cs = v dr, ce = v ss 2.0 - - v i ddr data retention current cs = v dr , v dr = 2.0v - 0.05 4 ma ce = v ss figure 5: data retention characteristics
ma9264 4/15 ac characteristics conditions of test for tables 5 and 6: 1. input pulse = v ss to 3.0v (ttl) and v ss to 4.0v (cmos). 2. times measurement reference level = 1.5v. 3. input rise and fall times 5ns. 4. output load 1ttl gate and cl = 60pf. 5. transition is measured at 500mv from steady state. 6. this parameter is sampled and not 100% tested. notes for tables 6 and 7: characteristics apply to pre-radiation at t a = -55 c to +125 c with v dd = 5v 10% and to post 100k rad(si) total dose radiation at t a = 25 c with v dd = 5v 10%. group a subgroups 9, 10, 11. max9264x70 max9264x95 symbol parameter min max min max units t avavr read cycle time 70 - 95 - ns t avqv address access time - 65 - 90 ns t ehqv chip select access time - 70 - 95 ns t slqv chip enable access time - 70 - 95 ns t ehqx (5,6) chip selection to output in low z 15 - 15 - ns t slqx (5,6) chip enable to output in low z 15 - 15 - ns t elqz (5,6) chip deselection to output in high z 0 20 0 20 ns t shqz (5,6) chip disable to output in high z 0 20 0 20 ns t axqx output hold from address change 30 - 40 - ns t glqv output enable access time - 25 - 30 ns t glqx (5,6) output enable to output in low z 15 - 15 - ns t ghqz (5,6) output enable to output in high z 0 20 0 20 ns figure 6: read cycle ac electrical characteristics max9264x70 max9264x95 symbol parameter min max min max units t avavw write cycle tlme 55 - 60 - ns t ehwh chip selection to end of write 50 - 60 - ns t slwh chip enable to end of write 50 - 60 - ns t avwh address valid to end of write 50 - 55 - ns t avwl address set up time 0 - 0 - ns t wlwh write pulse width 40 - 45 - ns t whav write recovery time 0 - 0 - ns t wlqz (5,6) wnte to output in high z 0 20 0 20 ns t dvwh data to write time overlap 25 - 30 - ns t whdx data hold from write 0 - 0 - ns t whqx (5,6) output active from end to write 0 20 0 20 ns figure 7: write cycle ac electrical characteristics
ma9264 5/15 symbol parameter conditions min. typ. max. units c in input capacitance v l = 0v - 3 5 pf c out output capacitance v i/o = 0v - 5 7 pf note: t a = 25 c and f = 1mhz. data obtained by characterisation or analysis; not routinely measured. figure 8: capacitance symbol parameter conditions f t basic functionality v dd = 4.5v - 5.5v, freq = 1mhz v il = v ss , v ih = v dd , v ol 1.5v, v oh 3 1.5v temp = -55 c to +125 c, gps pattern set group a subgroups 7, 8a, 8b figure 9: functionality subgroup definition 1 static characteristics specified in tables 4 and 5 at +25 c 2 static characteristics specified in tables 4 and 5 at +125 c 3 static characteristics specified in tables 4 and 5 at -55 c 7 functional characteristics specified in table 9 at +25 c 8a functional characteristics specified in table 9 at +125 c 8b functional characteristics specified in table 9 at -55 c 9 switching characteristics specified in tables 6 and 7 at +25 c 10 switching characteristics specified in tables 6 and 7 at +125 c 11 switching characteristics specified in tables 6 and 7 at -55 c figure 10: definition of subgroups
ma9264 6/15 timing diagrams figure 11b: read cycle 2 figure 11a: read cycle 1 1. we is high for read cycle. 2. device is continually selected. cs , oe low, ce high. 1. we is high for read cycle. 2. address vaild prior to or coincident with cs transition low or ce transition high. t avavr t avqv t axqx t slqv t slqx t shqz address cs data out high impedance data valid t ehqx t ehqv t elqz ce t glqx t glqv t ghqz oe t avavr t avqv t axqx address data out data valid
ma9264 7/15 figure 12: write cycle address t avavw t avwh t avwl t wlwh (2) t whav (3) (4) t wlqz we t axqx t wlqx data out (6) (7) high impedance data valid data in t dvwh t whdx t slwh t ehwh cs ce (5) (8) 1. we must be high during all address transitions. 2. a write occurs during the overlap (t wlwh ) of a low cs , a high ce and a low we . 3. t whav is measured from either cs or we going high or ce going low, whichever is the earlier, to the end of the write cycle. 4. if the cs low or ce high transition occurs simultaneously with, or after, the we low transition, the output remains in the high impedance state. 5. data out is in the active state, so data in must not be in the opposing state. 6. data out is the write data of the current cycle, if selected. 7. data out is the read data of the next address,if selected. 8. oe is low. (if oe is high then data out remains in the high impedance state throughout the cycle).
ma9264 8/15 typical performance characteristics max9264x70 55 53 51 49 47 45
ma9264 9/15 72 68 64 60 56 52 48 44 40 64 62 60 58 56 54 52 50
ma9264 10/15 25 20 15 10 5 16 14 12 10 8 6 4 2 58 57 56 55 54 53 52 51 50 49 48
ma9264 11/15 outlines and pin assignments figure 13: 28-lead ceramic dil (solder seal) - package style c d w a e b z h a 1 15 m e c e 1 seating plane 1 14 28 15 28 vcc 27 w 26 ce 25 a8 24 a9 23 a11 22 oe 21 a10 20 cs 19 d/q7 18 d/q6 17 d/q5 16 d/q4 15 d/q3 1 nc 2 a12 3 a7 4 a6 5 a5 6 a4 7 a3 8 a2 9 a1 10 a0 11 d/q0 12 d/q1 13 d/q2 14 gnd top view ref millimetres inches min. nom. max. min. nom. max. a - - 5.715 - - 0.225 a1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 c 0.20 - 0.36 0.008 - 0.014 d - - 36.02 - - 1.418 e - 2.54 typ. - - 0.100 typ. - e1 - 15.24 typ. - - 0.600 typ. - h 4.71 - 5.38 0.185 - 0.212 me - - 15.90 - - 0.626 z - - 1.27 - - 0.050 w - - 1.53 - - 0.060 xg404
ma9264 12/15 figure 14: 28-lead ceramic flatpack (solder seal) - package style f ref millimetres inches min. nom. max. min. nom. max. a - - 3.18 - - 0.125 q 0.66 - - 0.026 - - b 0.38 - 0.48 0.015 - 0.019 c 0.10 - 0.18 0.004 - 0.007 d 18.08 - 18.49 0.712 - 0.728 e - 1.27 - - 0.050 - l 7.62 - 9.91 0.300 - 0.390 m 12.50 - 12.09 0.492 - 0.508 xg530 m b e d l a q c pin 1 z m e 1nc 2 a12 3a7 4a6 5a5 6a4 7a3 8a2 9a1 10 a0 11 d/q0 12 d/q1 13 d/q2 14 gnd 28 vcc 27 w 26 ce 25 a8 24 a9 23 a11 22 oe 21 a10 20 cs 19 d/q7 18 d/q6 17 d/q5 16 d/q4 15 d/q3 bottom view
ma9264 13/15 function pin number option d and f via s ta tic 1 static 2 dynamic radiation a12 2 r 5v 0v f14 5v a7 3 r 5v 0v f7 5v a6 4 r 5v 0v f9 5v a5 5 r 5v 0v f8 5v a4 6 r 5v 0v f11 5v a3 7 r 5v 0v f10 5v a2 8 r 5v 0v f5 5v a1 9 r 5v 0v f4 5v a0 10 r 5v 0v f3 5v d/q0 11 r 5v 0v f1 5v d/q1 12 r 5v 0v f1 5v d/q2 13 r 5v 0v f1 5v gnd(vss) 14 direct 0v 0v 0v 0v d/q3 15 r 5v 0v f1 5v d/q4 16 r 5v 0v f1 5v d/q5 17 r 5v 0v f1 5v d/q6 18 r 5v 0v f1 5v d/q7 19 r 5v 0v f1 5v csb 20 r 5v 0v f15 5v a10 21 r 5v 0v f2 5v oeb 22 r 5v 0v f15 5v a11 23 r 5v 0v f6 5v a9 24 r 5v 0v f13 5v a8 25 r 5v 0v f12 5v ce 26 r 5v 0v f15b 5v wb 27 r 5v 0v f0 5v vdd 28 direct 5v 5v 5v 5v 1. f0=150khz, f1=f0/2, f2=f0/4, f3=f0/8 etc. 2. static 1, static 2 and dynamic: r=4k7. 3. radiation: r=10k. figure 15: burnin and radiation configuration
ma9264 14/15 radiation tolerance total dose radiation testing for product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. the sample devices will be subjected to the total dose radiation level (cobalt-60 source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. electrical tests, pre and post irradiation, will be read and recorded. dynex semiconductor can provide radiation testing compliant with mil-std-883 test method 1019, ionizing radiation (total dose). ion let (mev.cm 2 /mg) upset bit cross-section (cm 2 /bit) figure 17: typical per-bit upset cross-section vs ion let single event upset characteristics total dose (function to specification)* 1x10 5 rad(si) transient upset (stored data loss) 5x10 10 rad(si)/sec transient upset (survivability) >1x10 12 rad(si)/sec neutron hardness (function to specification) >1x10 15 n/cm 2 single event upset** 4.3x10 -11 errors/bit day latch up not possible * other total dose radiation levels available on request ** worst case galactic cosmic ray upset - interplanetary/high altitude orbit figure 16: radiation hardness parameters
ma9264 15/15 ordering information for details of reliability, qa/qc, test and assembly options, see manufacturing capability and quality assurance standards section 9. unique circuit designator s r q radiation hard processing 100 krads (si) guaranteed 300 krads (si) guaranteed for radiation levels above thos e stated please contact marketing radiation tolerance c f l n ceramic dil (solder seal) flatpack (solder seal) leadless chip carrier naked die package type qa/qci process (see section 9 part 4) test process (see section 9 part 3) assembly process (see section 9 part 2) l c d e b s rel 0 rel 1 rel 2 rel 3/4/5/stack class b class s reliability level max9264xxxxxxxx t c ttl cmos 70 95 70ns speed 95ns speed customer service centres france, benelux, italy and spain tel: +33 (0)1 69 18 90 00. fax: +33 (0)1 64 46 54 50 north america tel: 011-800-5554-5554. fax: 011-800-5444-5444 uk, germany, scandinavia & rest of world tel: +44 (0)1522 500500. fax: +44 (0)1522 500020 sales offices france, benelux, italy and spain tel: +33 (0)1 69 18 90 00. fax: +33 (0)1 64 46 54 50 germany tel: 07351 827723 north america tel: (613) 723-7035. fax: (613) 723-1518. toll free: 1.888.33.dynex (39639) / tel: (831) 440-1988. fax: (831) 440-1989 / tel: (949) 733-3005. fax: (949) 733-2986. uk, germany, scandinavia & rest of world tel: +44 (0)1522 500500. fax: +44 (0)1522 500020 these offices are supported by representatives and distributors in many countries world-wide. ? dynex semiconductor 2000 publication no. ds3692-7 issue no. 7.0 january 2000 technical documentation C not for resale. printed in united kingdom headquarters operations dynex semiconductor ltd doddington road, lincoln. lincolnshire. ln6 3lf. united kingdom. tel: 00-44-(0)1522-500500 fax: 00-44-(0)1522-500550 dynex power inc. unit 7 - 58 antares drive, nepean, ontario, canada k2e 7w6. tel: 613.723.7035 fax: 613.723.1518 toll free: 1.888.33.dynex (39639) this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design or price of any product or service. information con cerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to f ully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. all brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respec tive owners. http://www.dynexsemi.com e-mail: power_solutions@dynexsemi.com datasheet annotations: dynex semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. the annota tions are as follows:- target information: this is the most tentative form of information and represents a very preliminary specification. no actual design work on the product has been started. preliminary information: the product is in design and development. the datasheet represents the product as it is understood but details may change. advance information: the product design is complete and final characterisation for volume production is well in hand.

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